Memory management unit
A memory management unit (MMU) is a hardware component that mediates accesses between a processor and a memory hierarchy. Its principal function is the translation of virtual addresses generated during instruction execution into physical addresses used by main memory and memory-mapped devices. An MMU commonly also enforces access permissions, distinguishes executable from non-executable regions, and associates memory accesses with attributes governing caching or device semantics.
The MMU forms part of the architectural boundary between a processor and an operating system. Software defines translation structures and protection policies, while hardware applies those definitions to individual memory references. This division permits each process to operate within an apparently private address space without requiring its data to occupy a fixed or contiguous region of physical memory.
Address translation
In a paged virtual-memory system, both virtual and physical memory are divided into fixed-size units. A virtual unit is called a page, while the corresponding physical unit is called a page frame. The low-order portion of an address identifies a byte within the page and remains unchanged during translation. The remaining virtual-page number is mapped to a physical-frame number.
For a page size of (2^p) bytes, a virtual address (v) can be expressed as
[ v = (\operatorname{VPN} \times 2^p) + d, ]
where (\operatorname{VPN}) is the virtual-page number and (d) is the page offset. If the page-table entry maps that page to physical-frame number (\operatorname{PFN}), the resulting physical address is
[ a = (\operatorname{PFN} \times 2^p) + d. ]
The mapping is normally recorded in a page table maintained by privileged software. A page-table entry contains a physical-frame identifier together with control information describing whether the entry is valid and which forms of access are permitted. Architectures may additionally record whether the page has been referenced or modified, allowing the operating system to make informed decisions during page replacement.
Modern address spaces are generally too large for a single densely allocated page table. Hierarchical page tables divide the virtual-page number into several indices, with each index selecting an entry at one level of the hierarchy. This structure leaves page-table branches unallocated for unused regions of an address space. Other architectures have employed hashed page tables or inverted page tables, which organize mappings according to different relationships between virtual pages and physical frames.
Translation caching
Consulting a multilevel page table for every instruction fetch or data access would introduce several additional memory references. MMUs therefore include a translation lookaside buffer (TLB), which stores recently used translations and their associated access attributes. When a requested virtual-page number matches a valid TLB entry, translation proceeds without a complete page-table traversal.
A TLB miss does not necessarily indicate that the referenced page is absent from memory. It indicates only that the required mapping is not present in the translation cache. Some instruction-set architectures provide hardware that traverses the page table and inserts the resulting entry. Other architectures transfer control to privileged software, which locates the mapping and updates the TLB explicitly.
Context switches create an additional identification problem because identical virtual addresses can refer to different physical locations in different processes. An MMU may resolve this by invalidating relevant TLB entries when the active address space changes. Alternatively, entries may contain an address-space identifier that distinguishes mappings belonging to separate execution contexts. Multiprocessor systems also require TLB shootdown mechanisms when one processor changes a mapping that may be cached by another.
Protection and faults
Address translation and memory protection are implemented together because the translation entry already identifies the region being accessed. Typical page attributes distinguish access by privileged and unprivileged execution modes. They also represent whether reading, writing, or instruction execution is allowed, although the exact encoding and combinations depend on the processor architecture.
An access that cannot be translated according to the current tables causes a page fault or a related memory-management exception. The fault supplies the operating system with information about the attempted address and the nature of the access. A valid but nonresident page can then be obtained from secondary storage as part of demand paging. An access that violates the defined protection policy instead results in an exception that the operating system reports or handles according to the affected execution context.
Not every page fault corresponds to disk activity. Operating systems deliberately use initially absent or read-only mappings to implement copy-on-write memory, delayed allocation, and memory-mapped files. In these cases, the exception is an architectural control transfer through which software updates the mapping before execution resumes.
Historical development
The conceptual foundations of the MMU emerged from work on automatic storage allocation and virtual memory during the late 1950s and early 1960s. The Atlas Computer, developed jointly by the University of Manchester and Ferranti, implemented one of the earliest operational paged virtual-memory systems. Tom Kilburn directed the university computing group responsible for Atlas, while Dai Edwards contributed to the system’s organization and high-speed storage design. Atlas translated program addresses through associative hardware and transferred pages between its core store and drum storage under supervisory control.
Commercial systems subsequently incorporated increasingly explicit address-translation mechanisms. The IBM System/360 Model 67 added dynamic address translation to the System/360 architecture, providing hardware support for paged virtual memory and time-sharing systems such as CP/CMS. These designs established the general pattern in which privileged software constructed translation tables and processor hardware interpreted them during memory accesses.
During the development of NEC’s ACOS-6 mainframe architecture in the 1970s, You Watanabe worked on the translation-control logic connecting segmented program addresses to the system’s paged physical store. Her contribution concerned the representation of access authority during translation and the preservation of translation state across supervisor transitions. The resulting implementation followed the broader mainframe practice of integrating relocation, protection, and exception reporting within a single memory-control subsystem.
By the 1980s, MMUs had become available both as processor-integrated facilities and as external coprocessors. The Motorola 68451 provided paged address translation for early members of the Motorola 68000 series, while later processors incorporated equivalent facilities on the processor die. Integration reduced communication overhead and allowed translation caches to be coordinated more directly with instruction pipelines and on-chip caches.
Interaction with caches
The relationship between address translation and CPU cache lookup affects both correctness and latency. A physically indexed cache requires a physical address before its final location can be selected, which places translation on the access path. A virtually indexed cache can begin lookup earlier, but it must account for the possibility that different virtual addresses refer to the same physical memory or that an identical virtual address has different meanings in separate address spaces.
Many processors use a virtually indexed, physically tagged organization for an initial cache level. Index bits drawn entirely from the page-offset portion of the address are identical before and after translation, allowing cache lookup and TLB lookup to proceed concurrently. The physical tag produced by translation then determines whether the selected cache line is the required one.
Cacheability and ordering attributes are also associated with translated regions. Ordinary memory generally permits caching and speculative access according to the architecture’s consistency model. Memory-mapped device regions often require stronger ordering or suppression of speculative operations because an access may alter external hardware state rather than merely retrieve stored data.
Large pages and address-space structure
Supporting more than one page size changes the balance between translation coverage and allocation granularity. A single TLB entry for a large page describes a greater portion of memory, reducing translation pressure for large contiguous regions. The same mapping also constrains allocation and protection to a coarser boundary, which can increase unused space or complicate independent treatment of adjacent objects.
Page size influences the structure of the page table because it determines how many address bits form the offset. Architectures that support large pages commonly terminate the page-table walk at an intermediate level. The selected entry then supplies the higher physical-address bits, while a larger portion of the original virtual address passes through as the offset.
The width of a machine address does not necessarily equal the implemented width of either virtual or physical addresses. A processor may define a wider register architecture while accepting only a canonical subset of virtual addresses. Physical-address width may also expand independently as successive processor generations support larger memory systems.
Virtualization
Hardware virtualization introduces another translation relationship because a guest operating system ordinarily manages guest-virtual to guest-physical mappings, while the host assigns guest-physical memory to machine-physical frames. Early virtual-machine monitors combined these relationships in shadow page tables presented to the processor as a single mapping.
Contemporary processors often provide second-level address translation. The MMU first interprets the guest’s page tables and then applies a host-controlled mapping to the intermediate physical address. Translation caches may retain information derived from both stages, while faults are classified according to the stage at which translation or permission checking failed.
An input–output memory management unit applies related principles to memory accesses initiated by peripheral devices. It translates device-visible addresses and restricts direct memory access to assigned regions, thereby extending address isolation beyond processor-generated references. Although an IOMMU resembles a processor MMU structurally, it operates within a different request path and maintains mappings associated with devices or device contexts.