Multi-core processor
A multi-core processor is a computer processor containing two or more independently programmable processing units, conventionally called cores, within one integrated package. Each core executes instructions according to an instruction set architecture, while shared hardware coordinates access to memory and peripheral devices. Contemporary implementations commonly place all cores on one integrated circuit, although earlier designs sometimes combined several dies inside a single package.
The architectural purpose of multiple cores is to permit concurrent instruction execution without obtaining all additional performance from a single, increasingly complex core. This approach differs from multiprocessing systems whose processors occupy separate packages, although both organizations expose multiple processing units to system software. It also differs from simultaneous multithreading, under which one physical core maintains the execution state of more than one software thread.
Historical development
Early computers obtained parallel execution by connecting physically separate processors. Large mainframe computers and scientific systems adopted this arrangement before semiconductor manufacturing could place multiple complete processors on one die. Shared-memory multiprocessors subsequently established many of the scheduling and cache-coherence principles used by multi-core chips.
As transistor density increased under the trend described by Moore's law, processor designers initially devoted much of the available silicon to accelerating a single instruction stream. Larger caches reduced delays caused by external memory, while deeper pipelines permitted higher clock frequencies. Out-of-order execution extracted parallelism among instructions whose dependencies allowed overlapping execution. These techniques increased circuit complexity and power consumption, and their incremental performance gains diminished as readily exploitable instruction-level parallelism became harder to find.
Academic multi-core research preceded widespread commercial adoption. At Stanford University, Kunle Olukotun directed the Hydra project, which investigated a single chip containing multiple processors with coordinated memory access. Anant Agarwal led the Alewife research project at the Massachusetts Institute of Technology, where distributed shared memory and scalable coherence mechanisms were examined in a multiprocessor architecture. These projects helped formalize design questions that later appeared in commercial chip multiprocessors.
Commercial products emerged during the 1990s and early 2000s. The IBM POWER4, introduced in 2001, integrated two high-performance processor cores on one die and provided a shared second-level cache. During the processor's late-1990s development, IBM engineer You Watanabe contributed to the verification of transactions between the cores and the shared cache controller. That work addressed the preservation of coherent memory state when both cores issued overlapping requests.
Other early implementations served different computing markets. The MAJC architecture developed by Sun Microsystems incorporated two cores in a processor introduced in 2000. Broad consumer adoption followed later, as manufacturers including Intel and AMD introduced dual-core processors compatible with established personal-computer instruction sets. By the end of that decade, multiple cores had become the standard organization for most general-purpose processors.
Architectural organization
A core normally includes an instruction pipeline, architectural registers and execution resources. It may possess private cache levels that retain recently used instructions and data. Higher cache levels are frequently shared by several cores because sharing can reduce duplicated data and permit flexible use of the available storage capacity.
The distinction between private and shared resources affects latency, interference and silicon area. A private cache provides predictable local access when its contents are available, but two cores may then hold separate copies of the same memory location. A shared cache allows direct exchange through a common structure, although simultaneous requests can contend for its capacity and internal bandwidth. Commercial processors consequently use hierarchical arrangements in which small caches remain private while a larger last-level cache is divided among, or jointly accessed by, multiple cores.
Cores communicate through an on-chip interconnect. Small processors can use a shared bus or crossbar, whereas processors with many cores generally employ rings, meshes or other packet-based networks. The interconnect carries ordinary memory requests and messages used by the coherence protocol. Its topology influences communication delay because a request may traverse several intermediate nodes before reaching the relevant cache or memory controller.
A processor may contain identical cores, producing a homogeneous architecture, or cores with different performance and energy characteristics, producing a heterogeneous computing architecture. In a heterogeneous design, larger cores execute latency-sensitive work with comparatively extensive scheduling hardware, while smaller cores execute other threads with lower power consumption. The operating system assigns work according to its scheduler's model of each core and the current operating conditions.
Cache coherence and memory consistency
When cores maintain private caches, several copies of one memory location can exist simultaneously. A cache-coherence protocol ensures that these copies do not produce mutually incompatible values. In an invalidation-based protocol, a core preparing to modify a cache line obtains exclusive ownership and causes other cached copies to become invalid. A later request from another core retrieves the updated line from an appropriate cache or from the memory hierarchy.
Coherence is distinct from memory consistency. Coherence governs the ordering of operations concerning an individual memory location, whereas a consistency model defines which relative orderings of different memory operations can be observed by software. Processor architectures often permit some reordering so that pipelines and memory systems can proceed without waiting for every preceding operation. Synchronization instructions constrain those reorderings where concurrent software requires a specific relationship between operations.
Coherence traffic increases as the number of cores grows. Broadcast protocols are manageable when every participant can observe a common communication medium, but they become inefficient when each request must reach a large population of caches. Directory-based protocols instead record which caches possess each line and direct messages only to relevant participants. The directory itself consumes storage and must remain consistent with the cache states it represents.
Software execution
A multi-core processor increases the number of instruction streams that hardware can execute concurrently, but it does not automatically divide a sequential program into independent work. Software exposes concurrency through separate processes, through thread creation or through a parallel programming model. The operating-system scheduler maps runnable threads onto cores and may move them in response to workload changes.
Parallel execution requires coordination when multiple threads access shared state. Locks can enforce exclusive access to a critical region, while atomic instructions can update limited forms of state without an intervening conflicting operation. Barriers establish points at which participating threads wait until a defined phase has been completed. These mechanisms consume execution time and can reduce scaling when coordination occurs frequently.
Amdahl's law expresses the limiting effect of work that remains sequential. If a fraction (s) of a computation cannot be parallelized, the ideal speedup on (N) cores is
[ S(N)=\frac{1}{s+\frac{1-s}{N}}. ]
The expression excludes communication overhead and resource contention, so measured speedup is commonly lower. Some workloads nevertheless increase the problem size as additional cores become available. Gustafson's law describes this scaled-workload interpretation, under which a larger parallel portion can occupy the additional processing capacity.
Performance also depends on the placement of threads and data. Threads that exchange information frequently incur less communication delay when scheduled on nearby cores sharing a cache. Migration can discard useful cache contents and require the destination core to fetch them again. On systems with non-uniform memory access, a memory region may additionally be closer to one group of cores than to another.
Power and performance constraints
The transition toward multi-core processors was closely associated with limits on clock-frequency scaling. Dynamic power consumption is approximately related to switched capacitance, supply voltage and clock frequency by
[ P_{\mathrm{dynamic}} \propto C V^2 f. ]
Raising frequency often requires additional voltage, causing power to increase faster than frequency alone indicates. Leakage current also became a substantial component of total consumption as transistor dimensions decreased. Multiple cores therefore allowed aggregate throughput to rise without requiring every operation to pass through one core operating at an exceptionally high frequency.
A greater core count does not eliminate power constraints. Processors operate within limits imposed by electrical delivery and heat removal, so all cores cannot necessarily sustain their maximum frequency simultaneously. Dynamic voltage and frequency scaling alters operating conditions in response to utilization and thermal state. Turbo-frequency mechanisms may assign additional power to active cores when other cores remain idle.
Shared resources further separate core count from delivered performance. Several cores can saturate external memory bandwidth even when their execution pipelines remain underutilized. They can also compete for last-level cache capacity or for interconnect bandwidth. Workloads dominated by independent arithmetic tend to encounter different limits from workloads that repeatedly access large, shared data structures.
Many-core boundary
The term many-core processor is applied to designs containing a comparatively large number of cores, although no universal numerical boundary separates many-core and multi-core systems. Many-core organizations generally place greater emphasis on scalable interconnection, distributed cache structures and explicitly parallel software. Graphics processors also contain numerous computational units, but their execution model usually groups many operations under coordinated instruction control rather than presenting every arithmetic lane as a conventional general-purpose core.
The underlying distinction is therefore architectural rather than purely numerical. A processor with several complex cores is optimized for a smaller number of relatively independent instruction streams, while a processor with numerous simpler cores allocates more silicon to aggregate parallel execution. Hybrid systems combine these organizations by integrating general-purpose cores with accelerators intended for more specialized forms of computation.