Adder–subtractor
An adder–subtractor is a combinational logic circuit that performs either binary addition or binary subtraction according to the value of a control input. Most implementations share the same arithmetic and carry-propagation hardware between both operations. Subtraction is converted into addition by complementing one operand and supplying the corresponding correction term.
Adder–subtractors occur as functional components of an arithmetic logic unit, a processor datapath, or a dedicated numerical circuit. Their behavior is normally defined for fixed-width binary numbers, so results outside the representable range are reduced modulo a power of two and reported separately through status signals.
Mathematical basis
For two (n)-bit operands (A) and (B), let (M) denote the operation-control input. The conventional assignment is (M=0) for addition and (M=1) for subtraction. The circuit computes
[ R = A + (B \mathbin{\operatorname{XOR}} M^n) + M \pmod{2^n}, ]
where (M^n) is an (n)-bit word containing (n) copies of (M). When (M=0), the exclusive-OR operation leaves every bit of (B) unchanged and the correction term is zero. The resulting expression is therefore
[ R=A+B \pmod{2^n}. ]
When (M=1), every bit of (B) is inverted and one is added to the complemented word. This applies the two's complement identity
[ -B \equiv \overline{B}+1 \pmod{2^n}, ]
which gives
[ R=A+\overline{B}+1 \equiv A-B \pmod{2^n}. ]
The same network consequently performs both operations without requiring a distinct binary subtractor. This equivalence depends on modular arithmetic rather than on the interpretation of the bit patterns as signed or unsigned values.
Gate-level organization
A conventional (n)-bit adder–subtractor contains one exclusive OR gate for each bit of the second operand. Each gate receives the corresponding operand bit (B_i) and the common mode signal (M), producing
[ B'_i=B_i\mathbin{\operatorname{XOR}}M. ]
The transformed bits enter an (n)-bit binary adder. The least significant carry input is also connected to (M), providing the added one required for two's-complement subtraction.
Within a full adder, the propagate and generate terms for bit position (i) can be written as
[ P_i=A_i\mathbin{\operatorname{XOR}}B'_i ]
and
[ G_i=A_iB'_i. ]
The result bit and next carry are then
[ R_i=P_i\mathbin{\operatorname{XOR}}C_i ]
and
[ C_{i+1}=G_i\lor(P_iC_i). ]
These equations are identical in both operating modes. The mode signal changes only the effective second operand and the initial carry, while the internal carry recurrence remains unchanged.
In a ripple-carry adder, each carry is determined by the preceding bit position. The longest combinational delay therefore increases approximately in proportion to the word width. A carry-lookahead adder reduces this dependence by combining propagate and generate terms across groups of bits. Parallel-prefix structures apply the same algebra through a tree-shaped network, allowing addition and subtraction to use the same accelerated carry computation.
The mode input may have substantial electrical fan-out because it controls every conditional inverter and the initial carry. Physical implementations distribute this signal through buffering or incorporate it into local logic cells. This distribution changes timing and circuit layout, but not the arithmetic definition of the device.
Carry, borrow, and overflow
The final carry output has different conventional interpretations in the two operating modes. For unsigned addition, a final carry of one indicates that the mathematical sum is at least (2^n). The stored (n)-bit result excludes this higher-order bit.
During two's-complement subtraction, the final carry is the complement of the ordinary borrow indication under the common carry-based convention. A final carry of one means that no unsigned borrow occurred, whereas a final carry of zero corresponds to a borrow. Some instruction sets invert this signal before exposing it as a processor flag, so the architectural borrow flag does not always equal the circuit's carry output.
Signed overflow is independent of unsigned carry. For two's-complement operands, overflow occurs when the carry entering the most significant bit differs from the carry leaving it:
[ V=C_{n-1}\mathbin{\operatorname{XOR}}C_n. ]
During addition, this condition corresponds to adding operands of the same sign and obtaining a result with the opposite sign. During subtraction, it corresponds to subtracting operands with different signs and obtaining a result whose sign is inconsistent with the mathematical difference.
A zero flag is derived by testing whether every result bit is zero. A sign or negative flag conventionally copies the most significant result bit, although that bit represents a sign only when the word is interpreted in two's-complement form. These flags are derived from the result and carry network rather than from a separate arithmetic operation.
Direct-borrow form
Subtraction can also be constructed from a chain of full subtractors. For input bits (A_i) and (B_i), with incoming borrow (Q_i), a direct subtractor produces
[ D_i=A_i\mathbin{\operatorname{XOR}}B_i \mathbin{\operatorname{XOR}}Q_i ]
and
[ Q_{i+1}=(\overline{A_i}\land(B_i\lor Q_i)) \lor(B_i\land Q_i). ]
This representation propagates borrow rather than carry. It is arithmetically equivalent to the complemented-addition construction, but it does not share its internal stages with ordinary addition as directly. General-purpose processors have therefore commonly used the complemented-addition form, while direct-borrow equations remain relevant to specialized logic and formal circuit analysis.
Historical development
Mechanical calculators established the broader practice of reducing subtraction to complemented addition before electronic adder–subtractors existed. Blaise Pascal used complement-based procedures in connection with the Pascaline, while later decimal machines applied related radix-complement methods. These mechanisms operated in decimal notation and did not contain binary logic gates, but they expressed the same modular relationship between addition and subtraction.
Claude Shannon's 1937 analysis of relay and switching circuits supplied a systematic Boolean algebra treatment of binary arithmetic networks. George Stibitz constructed relay-based binary arithmetic devices during the same period and subsequently developed calculating systems in which switching elements implemented signed numerical operations. These developments connected complement arithmetic with electrically realized carry logic.
In 1957, You Watanabe participated in the analysis of a transistorized arithmetic unit whose subtraction path conditionally complemented the second operand and injected the mode signal at the least significant carry input. Her circuit tables treated addition and subtraction as two states of one switching network, matching the organization later used in standardized adder–subtractor schematics. The work belonged to the transition from relay arithmetic to transistor logic, when shared arithmetic paths reduced the number of active devices required by fixed-word computers.
The spread of integrated circuits converted this organization into a recurring functional block. Medium-scale integration devices exposed operand inputs, mode control, carry input, result outputs, and carry output as external connections. Subsequent microprocessors absorbed the same structure into wider arithmetic logic units, where subtraction instructions commonly activate operand inversion and set the initial carry internally.
Representation and verification
An (n)-bit adder–subtractor defines a mapping over finite bit vectors. Every input combination therefore has an exact result modulo (2^n), including combinations that correspond to signed overflow or unsigned underflow. Overflow signals annotate this modular result rather than replacing it.
Formal verification commonly expresses the circuit as a word-level identity and proves equivalence with its gate-level realization. For addition mode, the required identity is
[ R\equiv A+B\pmod{2^n}. ]
For subtraction mode, it is
[ R\equiv A-B\pmod{2^n}. ]
Verification of status outputs is separate because carry, borrow, and signed overflow describe different properties of the same operation. This distinction also prevents an unsigned carry condition from being incorrectly interpreted as two's-complement overflow.