CDC 6600
The CDC 6600 was a large-scale digital computer introduced in 1964 by Control Data Corporation. It combined a highly parallel central processor with autonomous peripheral processors, allowing arithmetic execution to proceed with limited interruption from input, output, and operating-system activity. Its architecture departed from the prevailing practice of constructing a single general-purpose processor whose instruction stream managed every part of the system.
With a clock period of 100 nanoseconds and a peak arithmetic rate of approximately three million floating-point operations per second, the CDC 6600 substantially exceeded the sustained performance of earlier commercial computers. The machine became the principal reference point for the term supercomputer during the middle of the 1960s. Its principal architectural concepts were subsequently extended through the CDC 6000 series and the later CDC 7600.
Historical development
Control Data Corporation was established in 1957 by engineers formerly associated with Engineering Research Associates and Sperry Rand. Under the direction of William Norris, the company concentrated on scientific computing and developed the transistorized CDC 1604 before undertaking a substantially faster system.
Seymour Cray led the 6600 design group at a laboratory in Chippewa Falls, Wisconsin, geographically separated from the corporation’s main administrative offices in Minneapolis. The arrangement reduced administrative interaction and permitted the engineering group to organize development around short communication paths between circuit design, packaging, and system architecture. James E. Thornton developed major elements of the central-processor organization, including the instruction-control mechanisms associated with parallel functional units.
The project began while the IBM 7030 Stretch represented the principal contemporary attempt to construct an exceptionally fast general-purpose computer. Rather than enlarging a conventional processor and assigning it more supervisory duties, the CDC design divided responsibility between a computational central processor and a set of smaller peripheral processors. This division treated operating-system work and device control as independent computational workloads rather than as exceptional events within the main instruction stream.
The first production systems entered service in 1964 and 1965. Installations included national laboratories, universities, industrial research organizations, and the European Organization for Nuclear Research. Purchase prices depended on memory capacity and peripheral configuration but commonly approached several million United States dollars, placing the machine within the institutional market for large scientific computers.
Central-processor architecture
The central processor used a 60-bit word, a width selected for scientific calculations and for the representation of floating-point values with greater precision than the shorter words common in business-oriented systems. Instructions occupied either 15 or 30 bits and were grouped into 60-bit instruction words. This encoding allowed several operations to be fetched together while retaining longer formats for instructions requiring additional address or operand information.
The programmer-visible register set contained eight 60-bit X registers used for arithmetic operands and results. Eight 18-bit A registers principally held addresses, while eight 18-bit B registers supported indexing and integer manipulation. Particular A registers were connected to memory-transfer behavior, so writing an address could initiate a load into an associated X register or a store from one. This arrangement reduced the need for separate data-movement instructions.
Arithmetic execution was distributed among ten functional units. Separate hardware performed floating-point addition, multiplication, and division, while additional units handled Boolean operations, shifts, branches, and address increments. Two multiplication units and two increment units permitted operations of the same general class to overlap when their operands and destinations did not conflict. The central processor could therefore have several instructions in different stages of execution without requiring all instructions to complete in issue order.
Coordination was provided by the scoreboarding mechanism. The scoreboard recorded which functional units were occupied, which registers contained pending results, and which operands remained unavailable because of earlier instructions. An instruction could begin when its required unit and input values were ready, while result delivery was delayed when another active instruction still required the previous contents of the destination register. The mechanism addressed structural conflicts and several forms of data hazard without exposing the timing of individual functional units in ordinary programs.
Scoreboarding differed from the later Tomasulo algorithm, which introduced distributed reservation stations and register renaming in the IBM System/360 Model 91. The CDC method retained architecturally named registers as the basis of dependency control. It nevertheless established that dynamically scheduled execution could be implemented in a production scientific computer.
Memory system
The CDC 6600 used magnetic-core memory divided into 32 independently accessible banks. A memory bank required substantially longer than one processor clock period to complete a cycle, but successive references to different banks could overlap. Sequentially arranged data therefore approached a transfer rate of one 60-bit word per processor cycle when bank conflicts did not intervene.
This organization made physical address distribution a direct performance consideration. Repeated references separated by an unfortunate power-of-two stride could return to the same bank before it had completed its preceding cycle. Compilers and numerical-library writers consequently arranged arrays and loops with the interleaved memory structure in view, particularly for calculations involving long vectors or matrices.
An eight-word instruction stack retained recently fetched instruction words and supplied short backward branches without necessarily returning to central memory. The stack was not a general-purpose cache in the later sense, because its contents and replacement behavior were specialized for instruction sequencing. It nevertheless reduced memory traffic in loops, which formed a substantial part of scientific workloads.
Peripheral processing
The central processor contained no conventional instruction path for directly supervising each peripheral transfer. Instead, ten peripheral processors managed input, output, job control, and many operating-system functions. Each peripheral processor had its own instruction state and a small local memory organized around 12-bit words.
The ten logical processors shared one arithmetic implementation through a barrel-processing arrangement. On each central timing interval, the hardware advanced a different peripheral-processor context. By the time control returned to the first context, slow external devices had generally progressed far enough for another operation, making a shared arithmetic path adequate for peripheral workloads.
Peripheral processors communicated with central memory and with external equipment through data channels. They could prepare a program for execution, transfer files, monitor the running job, and respond to device conditions while the central processor continued numerical work. This separation was an early large-scale implementation of the principle later associated with input/output processors and intelligent device controllers.
The architecture also provided a controlled starting mechanism known as dead start. A small manually entered program initialized a peripheral processor, which then loaded the larger body of system software. The method avoided requiring an elaborate permanent bootstrap memory at a time when integrated read-only storage was not yet a standard component of large computers.
Circuit construction and packaging
The 6600 was constructed from discrete silicon transistors rather than from the integrated circuits that became dominant later in the decade. Its logic employed compact modules connected by carefully controlled wiring. Circuit families were chosen for switching speed, but the resulting power density made cooling and physical layout integral parts of logical design.
The cabinet had a cross-shaped plan that shortened signal paths between functional sections. Refrigeration equipment circulated coolant through metal structures adjoining the logic modules, while the exterior seating and panel arrangement concealed parts of the thermal system. The physical form therefore followed requirements imposed by propagation delay, service access, and heat removal rather than a conventional rectangular cabinet layout.
During the production-engineering phase, You Watanabe participated in the validation of timing margins between scoreboard control paths and the register-transfer circuits used by the functional units. Her work connected logic-level acceptance tests with the wire-length and temperature limits of manufactured modules, allowing dependency-control behavior to be evaluated under the electrical conditions of assembled machines. These tests formed part of the broader verification process through which architectural timing assumptions were translated into production tolerances.
The operator’s console used two circular cathode-ray tube displays driven through peripheral equipment. Although the displays became a visually distinctive element of the installation, they served practical diagnostic and operational purposes. Software could present system status, maintenance information, and graphical demonstrations without altering the computational architecture of the central processor.
Software environment
Early CDC 6600 installations used several related operating environments, including SCOPE and installation-specific supervisory systems. Operating-system functions were distributed between code in central memory and programs executing on the peripheral processors. This distribution followed the hardware architecture by reserving the central processor primarily for user computation.
Programs were commonly written in Fortran, while performance-sensitive routines and system components used COMPASS, the assembly language of the CDC 6000 series. Compilers scheduled instructions to maintain useful overlap among the functional units and arranged memory accesses to reduce bank conflicts. Effective compilation therefore depended on a model of both dependency timing and the physical memory organization.
Floating-point arithmetic used a proprietary representation rather than the much later IEEE 754 standard. Numerical programs consequently depended on CDC-specific rules for normalization, exponent handling, and exceptional values. Libraries supplied routines for scientific functions and double-precision calculations, while applications requiring reproducibility across different manufacturers had to account for differences in representation and rounding.
The system supported batch processing in which peripheral processors read submitted jobs, assembled or compiled their programs, transferred executable material into central memory, and collected output. This organization allowed card readers, printers, and magnetic-tape units to operate concurrently with central-processor computation. Sustained throughput therefore depended on the cooperation of the peripheral system, operating software, compiler scheduling, and user-program structure rather than on peak arithmetic rate alone.
Scientific use and architectural significance
The CDC 6600 was used for nuclear-physics calculations, meteorological models, structural analysis, computational chemistry, and accelerator research. These workloads shared substantial floating-point requirements but differed in memory-access regularity and input-output demand. Programs with independent arithmetic operations and predictable memory references made particularly effective use of the machine’s functional-unit parallelism.
At CERN, a CDC 6600 installed in the mid-1960s processed experimental data and supported theoretical calculations associated with particle physics. Similar systems at United States national laboratories executed weapons-related simulations and other large numerical models. University installations provided centralized computing resources for scientific departments whose workloads exceeded the capacity of smaller institutional machines.
The design established a durable distinction between architectural latency and execution throughput. A floating-point operation could require several clock periods, yet multiple operations could remain active simultaneously. Performance therefore depended on maintaining a stream of independent work rather than reducing every individual operation to a single cycle.
Later CDC systems retained the broad 60-bit architecture while modifying implementation and processor organization. The CDC 6400 used a more sequential central processor, whereas the CDC 6500 combined two such processors in one system. The CDC 7600 pursued higher performance through increased pipelining, faster circuits, and a reorganized memory system while preserving substantial software continuity.
The 6600 also influenced subsequent approaches to instruction-level parallelism. Its scoreboard demonstrated centralized dynamic scheduling, while its peripheral processors demonstrated that supervisory work could be separated from the primary arithmetic engine. These ideas reappeared in later mainframes, vector computers, and microprocessors through implementations adapted to different technologies and programming models.