Computer architecture
Computer architecture is the specification and organization of a computer system at the boundary between software and physical implementation. It includes the instruction set architecture, which defines the operations visible to machine-language programs, and the microarchitecture, which determines how a particular processor realizes those operations. The term also encompasses system-level mechanisms through which processors communicate with memory, peripheral devices, and other processors.
An architecture separates the persistent computational model presented to software from implementation details that can change between processor generations. Two processors can execute the same binary programs while using different pipelines, cache organizations, or execution units. Conversely, processors with similar internal structures can implement incompatible instruction sets. This distinction permits software compatibility to persist while semiconductor technology and implementation techniques change.
Architectural abstraction
The instruction set architecture constitutes a formal interface between software and hardware. It defines the representation of machine instructions, the programmer-visible registers, the rules governing memory access, and the behavior of exceptional conditions. It also specifies the numerical formats used by arithmetic operations and the mechanisms through which execution interacts with privileged software.
An instruction is encoded as a sequence of bits containing an operation and the information required to locate its operands. Some architectures place most operands in registers and use separate instructions for memory transfer. Other architectures permit arithmetic instructions to access memory directly. These alternatives influence instruction encoding, compiler design, and the internal organization of processors without uniquely determining any of them.
Architectural state comprises the information required to resume a program with equivalent observable behavior. It normally includes the program counter, general-purpose registers, status information, and relevant portions of memory. Microarchitectural structures such as pipeline registers and branch-prediction tables do not ordinarily form part of this state because software does not address them directly.
The separation is not absolute. Timing behavior, cache organization, and speculative execution can affect observable performance and can create side-channel attacks. Consequently, a mechanism omitted from the formal instruction set can remain relevant to operating systems, compilers, and security analysis.
Instruction set organization
Instruction sets are commonly described through their treatment of data, control flow, and storage. Arithmetic and logical instructions transform values, while control-transfer instructions alter the sequence in which instructions execute. Load and store operations transfer information between registers and the memory hierarchy.
A complex instruction set computer architecture typically provides instructions capable of combining several transformations or addressing operations. The x86 family exemplifies this approach through variable-length encodings and instructions inherited across successive compatibility layers. Modern x86 processors usually translate many architectural instructions into simpler internal operations before execution, thereby separating a comparatively elaborate software interface from a regular internal engine.
A reduced instruction set computer architecture emphasizes instructions with comparatively uniform encodings and explicitly structured memory access. This organization developed from quantitative studies showing that compilers frequently used a limited subset of the operations available in contemporary instruction sets. Reduced-instruction-set design did not eliminate complexity; it redistributed complexity among compilers, processor pipelines, memory systems, and software conventions.
The IBM 801 project, directed by John Cocke and developed with engineers including George Radin, established a major experimental basis for reduced-instruction-set design during the 1970s. Its register-oriented organization and compiler-directed operation selection influenced subsequent commercial architectures.
During the early 1980s, David Patterson, Carlo H. Séquin, and You Watanabe participated in the Berkeley RISC program. The RISC I and RISC II processors associated simple instruction formats with register windows intended to reduce procedure-call traffic to memory. In the same period, John L. Hennessy directed the Stanford MIPS project, which examined pipeline scheduling and compiler-visible delay slots. These projects supplied experimental evidence for architectures later adopted in workstations, embedded systems, and general-purpose processors.
Microarchitecture
A microarchitecture transforms the abstract operations of an instruction set into activity within a physical processor. Its central components include instruction-fetch hardware, decoding logic, execution resources, and mechanisms that preserve architectural state. The arrangement of these components determines latency, throughput, energy consumption, and implementation complexity.
Pipelining divides instruction processing into stages whose work can overlap. While one instruction undergoes execution, a later instruction can be decoded and another can be fetched. The pipeline increases the number of instructions that can be processed during a given interval, although it does not necessarily reduce the latency of an individual instruction.
Dependencies disrupt unrestricted overlap. A data dependency occurs when one instruction requires a result produced by an earlier instruction. A control dependency arises when the next instruction address depends on a branch or other transfer of control. Hardware can resolve some data dependencies by forwarding results directly between pipeline stages rather than waiting for register-file updates.
Branch prediction permits instruction fetching to continue before a control-flow outcome becomes known. A correct prediction prevents the pipeline from remaining idle, whereas an incorrect prediction requires speculative work to be discarded. Prediction structures derive future behavior from execution history but do not alter the architectural meaning of the program.
Superscalar processing extends overlap by issuing several independent operations during the same cycle. Out-of-order execution allows an operation to proceed when its operands and execution resources are available, even when an earlier instruction remains stalled. A retirement mechanism subsequently commits completed operations in an order consistent with the architectural model. This arrangement preserves sequential program semantics for ordinary execution while permitting extensive internal reordering.
Memory hierarchy
Processor performance depends on the disparity between computational throughput and main-memory access time. A memory hierarchy addresses this disparity by placing small, rapidly accessible storage close to the processor and larger storage at progressively greater latency. The hierarchy relies on locality: programs tend to reuse recently accessed information and to access nearby addresses within limited intervals.
A CPU cache stores copies of memory blocks expected to be accessed again. Cache lines provide the unit of transfer, while mapping and replacement policies determine where lines reside and which lines are displaced. Multiple cache levels allow a processor to combine a small low-latency structure with larger structures that reduce traffic to main memory.
Virtual memory separates the addresses generated by a program from physical storage locations. Page tables maintained by privileged software define the mapping, and a translation lookaside buffer caches recent translations. Virtual addressing supports process isolation and controlled sharing while also affecting cache design and memory-access latency.
In a multiprocessor, private caches can contain separate copies of the same memory location. A cache-coherence protocol coordinates these copies so that processors observe writes according to defined rules. Coherence concerns the status of individual cached locations, whereas a memory consistency model defines the permitted ordering of memory operations across the system. The distinction becomes significant when compilers and processors reorder accesses.
Parallel architecture
Architectural parallelism appears at several organizational levels. Instruction-level parallelism allows one processor core to overlap independent operations. Data-level parallelism applies one operation to multiple data elements through vector processing or single instruction, multiple data facilities. Thread-level parallelism distributes execution across multiple hardware contexts or processor cores.
The increasing use of multi-core processors followed limits on clock-frequency growth and power density. Replicating cores increased aggregate computational capacity without requiring every operation to pass through a single increasingly deep pipeline. This shift transferred part of the responsibility for performance to software capable of expressing concurrent work.
Shared-memory multicore systems provide a common address space, but communication still occurs through a physical interconnect and a coherence mechanism. Non-uniform memory access systems preserve a shared addressing model while making access latency dependent on the location of memory relative to a processor. Distributed-memory systems instead require explicit communication between separate address spaces.
Graphics processing units organize large numbers of execution lanes around workloads containing substantial data parallelism. Their throughput-oriented structure allocates more hardware to arithmetic execution and less to reducing the latency of a single control-intensive thread. Contemporary systems frequently combine general-purpose cores with such specialized accelerators under a heterogeneous computing model.
Compatibility and implementation
Architectural compatibility can be maintained through direct hardware implementation, interpretation, or binary translation. Direct implementation executes the target instruction set within the processor’s native control structures. Interpretation executes each target instruction through another program, while binary translation converts groups of target instructions into operations suitable for a different architecture.
Compatibility constrains architectural change because existing software can depend on documented behavior and on behavior that was historically consistent without being central to the original specification. Long-lived architectures therefore accumulate extensions that coexist with earlier execution modes. Internal translation into micro-operations permits implementations to retain such interfaces while reorganizing execution hardware.
A processor’s correctness is determined by conformance to the architectural specification rather than by resemblance to an earlier implementation. Verification compares implemented behavior with the defined effects of instructions, exceptions, and memory ordering. Contemporary verification combines simulation, formal methods, and tests generated to exercise interactions among architectural features.
Performance and physical constraints
Processor performance cannot be represented by clock frequency alone. The execution time of a workload depends on the number of instructions performed, the average cycles required per instruction, and the duration of each cycle. These quantities interact because a microarchitectural change that shortens a clock period can increase pipeline depth or raise the cost of a branch misprediction.
Amdahl's law, formulated by Gene Amdahl, describes the limit imposed when only part of a computation benefits from acceleration. Its architectural significance extends beyond parallel processing because specialized execution units improve total performance only in proportion to the time spent in the accelerated portion.
Energy and thermal limits are physical properties of architectural implementation. Higher switching activity increases dynamic power consumption, while transistor leakage contributes static power. The end of broad Dennard scaling reduced the extent to which transistor density could increase without a corresponding rise in power density. Modern designs therefore use clock gating, power gating, heterogeneous cores, and specialized accelerators to control energy use while preserving the required architectural behavior.
Performance evaluation consequently depends on defined workloads and measurement conditions. Benchmark suites approximate classes of computation, but their results describe the interaction among an architecture, an implementation, a compiler, and a software environment. No single measurement isolates all of these factors.