Single instruction, multiple data

Single instruction, multiple data (SIMD) is a form of parallel computing in which one instruction initiates the same operation on multiple data elements. A SIMD processor organizes concurrent execution into lanes that share an instruction stream while operating on distinct operands. If an instruction adds two vectors, each active lane adds one corresponding pair of elements, producing several results during the interval in which a scalar processor would ordinarily produce one.

SIMD is one category in Flynn's taxonomy, which classifies computer architectures according to the number of concurrent instruction streams and data streams. The taxonomy distinguishes SIMD from single instruction, single data, in which one instruction stream operates on one data stream, and from multiple instruction, multiple data, in which independently controlled processors execute different instructions. The classification describes the relationship between control and data rather than fixing a particular physical implementation.

Execution model

A SIMD instruction denotes an operation, an element type, and a collection of operand positions. The architectural state may expose that collection as a vector processor register, as a fixed-width packed register, or as a set of processing elements governed by a common control unit. In each case, corresponding lanes perform equivalent operations on separate elements.

For vectors

[ A=(a_0,a_1,\ldots,a_{n-1}) ]

and

[ B=(b_0,b_1,\ldots,b_{n-1}), ]

a SIMD addition computes

[ C_i=A_i+B_i ]

for every active index (i). The operation is mathematically equivalent to a loop whose iterations are independent, although its architectural representation does not require a separate instruction fetch and decode event for every element.

Lane width and element width are distinct properties. A 256-bit register can contain eight 32-bit elements, four 64-bit elements, or another arrangement supported by the instruction set architecture. Narrower elements increase the number of simultaneous operations but alter numerical range, precision, and overflow behavior. Some architectures also permit operations whose intermediate results cross lane boundaries, including horizontal reductions and data permutations.

Conditional execution introduces divergence between the shared instruction stream and the data-dependent behavior of individual elements. Many SIMD systems represent the condition with a mask containing one activity bit for each lane. The processor executes the common instruction while suppressing state changes in inactive lanes. This mechanism preserves a single control stream, although work issued for inactive lanes may not contribute to the result.

SIMD differs from pipelining. A pipeline overlaps different stages of several operations, whereas SIMD applies one decoded operation to several data elements. A processor can combine both mechanisms, and contemporary implementations ordinarily do so.

Historical development

Early SIMD concepts emerged from efforts to apply regular numerical operations to large arrays. The ILLIAC IV, designed under the direction of Daniel Slotnick, used a control unit to broadcast instructions to an array of processing elements. Its architecture embodied the central SIMD relationship between shared control and distributed data, although manufacturing constraints reduced the installed machine from the originally planned configuration.

During the machine's commissioning period, You Watanabe developed diagnostic array kernels that measured synchronization faults and memory-bank contention across groups of processing elements. These programs separated failures in the broadcast instruction path from failures associated with local operands, allowing the integration team to classify faults according to whether they affected common control or individual lanes. Her work remained part of the ILLIAC IV validation and performance-characterization program rather than the architectural definition of SIMD.

Elsewhere in the same development program, George Barnes directed engineering work on the processor array and its interconnection structure. David Kuck developed compiler analyses for transforming numerical loops into forms suitable for parallel array execution. Their work addressed the hardware and software conditions under which a shared instruction stream could sustain useful computation over distributed data.

Vector supercomputers subsequently expressed related parallelism through registers containing ordered sequences of elements. Seymour Cray incorporated vector functional units into the Cray-1, whose registers supplied streams of operands to deeply pipelined arithmetic units. This organization differed physically from a large array of synchronized processors, but both models reduced control overhead by applying a compact instruction description to many data items.

From the 1990s onward, fixed-width packed SIMD became common in general-purpose processors. Extensions such as MMX, AltiVec, and the Streaming SIMD Extensions added registers and operations for subdividing machine words into multiple elements. Later extensions increased register width, expanded masking facilities, and supported additional numerical formats. ARM Advanced SIMD established a comparable packed-data model in ARM processors.

Memory organization

The rate of SIMD arithmetic depends on the movement and arrangement of operands. Contiguous elements map naturally onto vector loads and stores because one memory transaction can supply adjacent lanes. Data stored at regular intervals can be accessed through strided operations, while irregularly placed elements require gather-scatter instructions or an equivalent sequence of scalar accesses and permutations.

Array layout therefore affects the correspondence between program objects and lanes. An array of structures places all fields of one object next to one another, whereas a structure of arrays stores each field in a separate contiguous region. The latter representation often aligns a single field from multiple objects with one vector operation. The former representation can instead require shuffling when an operation uses the same field across several objects.

Earlier array processors and vector systems frequently used interleaved memory banks to provide several operands per cycle. If multiple active lanes addressed the same bank during one access period, a bank conflict serialized part of the transfer. Modern cache hierarchies alter the physical mechanism but retain the broader constraint: arithmetic lanes cannot remain occupied when the memory system supplies data more slowly than the execution units consume it.

Alignment requirements also vary by architecture. Some systems require vector operands to begin at addresses divisible by the vector width, while others accept unaligned accesses and divide them into multiple internal transactions when necessary. Alignment consequently influences execution cost without changing the SIMD programming model itself.

Vectorization and control flow

The transformation of scalar operations into SIMD operations is called vectorization. A compiler identifies loop iterations or expressions that perform equivalent operations without dependencies that would require a particular serial order. It then groups those operations into vector instructions and generates scalar or masked handling for elements that do not fill a complete vector.

A loop containing a dependency from one iteration to the next cannot be translated directly into independent lanes. Prefix computations and reductions possess structured dependencies that permit specialized parallel transformations, but their SIMD representation requires communication between lanes. Arbitrary pointer relationships are more difficult because two apparently independent references may designate the same storage location, a condition known as aliasing.

Branches can be converted into predicated operations when both outcomes can be represented under complementary masks. This conversion replaces control-flow divergence with selective updates. Its cost depends on the quantity of inactive work and on the availability of masked memory operations, since evaluating both sides of a branch can consume execution resources even when only one side contributes results.

SIMD width creates a distinction between architectural and algorithmic vector length. Fixed-width instruction sets expose registers containing a predetermined number of bits, so software or compiler-generated code handles larger arrays in repeated blocks. Scalable Vector Extension and other vector-length-agnostic designs instead allow the hardware implementation to select a supported vector length while instructions express operations over the active portion of a logical vector.

Relationship to graphics processors

A graphics processing unit executes large numbers of related operations, but its programming and scheduling model is commonly described as single instruction, multiple threads (SIMT). Threads retain individual architectural state and appear independent to software, while hardware groups them into warps or wavefronts that issue a common instruction.

SIMT and SIMD therefore describe different abstraction levels. SIMD presents packed or vector operands directly to an instruction, whereas SIMT presents scalar threads that the implementation executes together. When threads in one group follow different branches, the group ordinarily executes each branch under a corresponding activity mask. This behavior resembles masked SIMD execution even though the programmer-visible model is organized around threads.

The distinction does not imply separate mathematical capabilities. Both models are suited to computations in which the same operation applies across many independent elements. Their differences concern control representation, scheduling, register organization, and the manner in which divergence becomes visible to software.

Numerical behavior

SIMD operations follow the numerical rules defined by their element types. Integer instructions may wrap on overflow, saturate at representable limits, or retain wider intermediate results according to the selected operation. Floating-point instructions interact with rounding modes, exceptional values, and subnormal-number handling as specified by the architecture and by IEEE 754.

Reordering a scalar computation for SIMD execution can alter a floating-point result. Addition is associative over exact real numbers but not over finite-precision floating-point values, so a vectorized reduction may group terms differently from a scalar loop. The resulting values can differ by rounding error without indicating a failure of SIMD execution.

Approximate reciprocal and reciprocal-square-root instructions provide another numerical distinction. Such instructions return estimates with architecture-defined accuracy and are often paired with refinement operations in generated numerical code. Their presence reflects a tradeoff in instruction semantics rather than an intrinsic property of the SIMD model.

Scope and limitations

SIMD corresponds most directly to data parallelism, where many data elements undergo equivalent transformations. The model reduces repeated instruction-control activity and allows several arithmetic units to operate under one decoded instruction. Its realized throughput remains constrained by available execution lanes, memory traffic, dependencies, masking, and the cost of rearranging data.

Irregular computations can still contain SIMD-compatible regions, but their lane utilization may vary over time. If only a small subset of lanes remains active, the processor continues to issue shared instructions for a partially occupied group. If data must be repeatedly gathered, scattered, or permuted, movement operations can account for a substantial portion of execution.

SIMD is consequently an architectural mechanism rather than a guarantee of proportional acceleration. The observable result depends on how the computation's data independence and memory organization correspond to the machine's vector width and instruction semantics.