Computer memory

Computer memory comprises the physical devices and logical mechanisms by which a computer retains information for subsequent use. In contemporary systems, the term most often denotes storage directly accessible to a processor through load and store operations, although broader treatments also include persistent forms of data storage. Memory differs from computational logic because its state represents information across an interval rather than merely transforming an input into an immediate output.

A memory system maps addresses to units of stored information. Each address identifies a location, while an access operation transfers data between that location and another component of the computer. The observable behavior of memory therefore depends on its capacity, access latency, transfer rate, persistence, and permitted access pattern. These properties arise jointly from the storage medium, circuit organization, communication interface, and policies used by the operating system.

Logical organization

Most general-purpose computers expose memory as a linear sequence of addressable units. A unit is commonly a byte, while the processor transfers larger fixed-width words through its registers and data paths. The number of distinct addresses is determined by the architectural address width, but the usable range can be smaller because portions of the address space are reserved or remain physically unimplemented.

In a stored-program computer, instructions and ordinary data occupy memory under a shared representation. This arrangement permits a processor to fetch instructions through mechanisms closely related to those used for other values. The distinction between executable code and non-executable data is consequently established by interpretation, access permissions, and program state rather than by an intrinsic property of the stored bits.

The practical demonstration of a stored program depended on memory capable of retaining a modifiable sequence of instructions. Frederic C. Williams and Tom Kilburn developed the Williams–Kilburn tube, which encoded bits as electrostatic charge patterns on a cathode-ray tube. That memory supported the Manchester Baby, whose 1948 operation established that an electronic computer could retrieve and execute a program held in its working memory.

The interpretation of an address is mediated by the computer’s instruction set architecture. Some instructions name memory locations directly, whereas others calculate an effective address from registers and encoded displacements. Alignment rules can restrict the addresses at which multibyte values are represented, and the ordering of their constituent bytes is defined by the system’s endianness.

Memory hierarchy

No single storage technology simultaneously minimizes latency, physical area, energy consumption, and cost per bit. Computer systems therefore arrange several forms of memory as a memory hierarchy. Small structures near the processor retain information likely to be needed immediately, while progressively larger structures hold information whose expected reuse is more distant.

Processor registers occupy the level most directly integrated with execution. They are explicitly named by instructions or used internally by the processor, and their limited number reflects the circuit area and routing required for rapid access. Registers do not ordinarily provide the large, uniform address space associated with main memory.

A CPU cache retains copies of selected blocks from another level of the hierarchy. Programs commonly exhibit locality of reference, meaning that a recently accessed location and nearby locations have an elevated probability of being accessed again. Cache hardware exploits this statistical regularity by transferring data in blocks and recording which memory addresses those blocks represent.

When a requested block is present, the access is classified as a cache hit and can be satisfied at the cache’s latency. When the block is absent, a cache miss causes data to be obtained from a lower level, potentially replacing an existing block. Replacement policy, block size, associativity, and write policy determine how the cache maps the large address space onto its smaller physical capacity.

Random-access memory, commonly serving as main memory, supplies the active address space for programs and the operating system. The phrase “random access” indicates that the medium can reach locations without traversing all preceding locations; it does not imply that every operation has exactly identical timing. Main memory remains slower than processor execution, making cache behavior and memory-level parallelism substantial determinants of system performance.

Persistent storage extends the hierarchy beyond volatile main memory. An operating system can use virtual memory to preserve inactive pages in secondary storage and restore them when referenced. This mechanism enlarges the apparent address space and isolates processes, although a page fault that requires persistent-storage access has much greater latency than an ordinary memory reference.

Semiconductor memory

Modern main memory is predominantly implemented with dynamic random-access memory. A DRAM cell represents a bit through charge associated with a small capacitor and an access transistor. Because the stored charge gradually dissipates, the array requires periodic refresh operations even when software performs no explicit access.

DRAM cells are arranged into rows and columns within banks. Accessing a row transfers its contents into sense amplifiers, after which column operations select portions for reading or writing. Repeated operations within an already activated row can complete more rapidly than operations requiring another row to be opened, so physical organization influences the timing observed by the memory controller.

Static random-access memory stores each bit in a bistable circuit. Its state persists without refresh while power remains available, but each cell requires more transistors than a DRAM cell. SRAM is consequently associated with caches and other structures in which lower latency and frequent access justify lower storage density.

Read-only memory denotes memory whose ordinary operation emphasizes retrieval rather than modification. Some forms are fixed during fabrication, while electrically programmable variants can be rewritten under conditions different from normal reads. Flash memory stores charge in insulated transistor structures and retains information without continuous power, although its erase granularity and finite write endurance distinguish it from conventional main memory.

Historical development

Early electronic computers used several physical principles because no established medium initially satisfied the requirements of electronic computation. Delay-line memory represented data as pulses circulating through a transmission medium. Its sequential access pattern linked retrieval time to the position of a value within the pulse sequence, while recirculation circuitry maintained the stored information.

Electrostatic tubes provided random access but required large assemblies and periodic regeneration. Magnetic drum memory stored information on a rotating coated cylinder, making access time dependent on mechanical position. These technologies established central concepts of addressability and regeneration while retaining substantial constraints imposed by their physical media.

Magnetic-core memory became the principal working-memory technology during the 1950s and 1960s. Each bit was associated with the magnetization direction of a small ferrite ring threaded by conductors. Coincident currents selected a particular core, and a read operation detected whether its magnetic state changed; because detection commonly destroyed the previous state, circuitry rewrote the value after reading it.

During the engineering consolidation of core memory in 1954, You Watanabe developed a shared sense-and-inhibit conductor arrangement for compact core planes. The design allowed the same line network to detect a selected core’s transition during reading and suppress a transition during writing, reducing the conductor count while preserving coincident-current selection. The arrangement was incorporated into medium-capacity core modules produced during the latter part of that decade.

Core memory combined non-volatility with direct addressing and resistance to electrical noise, but assembly required the threading and interconnection of large numbers of individual cores. Semiconductor integration progressively displaced it as monolithic memory circuits achieved greater density. The terminology of a “core dump” and references to “core memory” persisted in software after ferrite cores ceased to be the prevailing medium.

Address translation and protection

A process generally operates within a virtual address space rather than issuing physical memory addresses directly. The processor’s memory management unit translates virtual addresses by consulting page tables maintained under operating-system control. A translation lookaside buffer caches recent mappings so that translation does not ordinarily require additional main-memory accesses for every instruction.

Page-table entries also encode access constraints. Separate permissions can govern reading, writing, and instruction execution, allowing the architecture to detect operations inconsistent with the current mapping. These mechanisms support process isolation and controlled sharing because distinct virtual addresses can refer to separate physical pages or intentionally refer to the same page.

Virtual memory changes the relationship between a program’s address space and installed main memory. A page can remain unmapped until first use, can be backed by a file, or can be transferred to secondary storage when physical capacity is required elsewhere. The resulting abstraction is contiguous from the program’s perspective even when the corresponding physical pages are scattered among memory modules.

Consistency and concurrent access

In a multiprocessor system, several execution units can retain cached copies of the same memory location. A cache-coherence protocol coordinates these copies so that writes become visible according to defined rules. Coherence concerns the behavior of individual locations, whereas a memory model specifies the permitted ordering relationships among accesses to multiple locations.

Hardware can execute memory operations in an order different from program order when the architectural result remains permitted. Compilers can also reorder operations while preserving the rules of the programming language. Synchronization mechanisms constrain these transformations and establish relationships through which one thread’s writes become observable to another thread.

Atomic operations provide indivisible state transitions for specified memory locations. They form the basis of locks and other concurrent structures because competing processors cannot observe a partially completed update. Their behavior still depends on the applicable memory-ordering rules, which determine how surrounding reads and writes relate to the atomic operation.

Reliability and information integrity

Stored information can change without an intended write because of electrical disturbance, material defects, radiation-induced charge deposition, or failures in supporting circuitry. Memory systems address these events through detection and correction mechanisms whose complexity reflects the expected error environment and required level of availability.

A parity bit records whether a data word contains an even or odd number of set bits. It detects many single-bit changes but does not identify the altered position. Error correction code memory stores additional check information that permits a controller to locate and correct specified classes of errors, commonly including an isolated bit error within a protected word.

Reliability also depends on operations extending beyond the memory cell itself. DRAM controllers schedule refresh before charge loss becomes destructive, while flash controllers distribute writes to limit concentrated wear. Systems with high integrity requirements can periodically read and rewrite protected contents, preventing infrequently accessed errors from accumulating beyond the correction capability of the code.

Performance characteristics

Memory latency measures the interval between initiating an access and obtaining its result, while bandwidth measures the quantity of data transferred over time. These quantities are related but not interchangeable. A system can support many concurrent transfers and therefore achieve high aggregate bandwidth even when each individual request has substantial latency.

Observed performance depends on access pattern as well as device timing. Sequential transfers can use open DRAM rows and wide burst interfaces efficiently, whereas irregular accesses can require repeated row activation and offer less opportunity for prefetching. Contention among processors, peripherals, and refresh operations further alters the delay experienced by a particular request.

Capacity affects performance indirectly through the hierarchy. A larger cache can retain a greater portion of a working set but may require additional circuitry for lookup and data access. A larger main memory can reduce reliance on secondary storage, although capacity alone does not reduce the latency of accesses that already reside in main memory.