Reduced instruction set computer

A reduced instruction set computer (RISC) is a central processing unit whose instruction-set architecture emphasizes operations that can be decoded and executed through comparatively regular datapaths. RISC designs commonly use a load–store architecture, in which explicit memory instructions transfer data between memory and registers while arithmetic instructions operate primarily on registers. The category originated from empirical studies showing that programs compiled from high-level languages relied heavily on a limited subset of the operations provided by contemporary processors.

The word “reduced” refers principally to a reduction in architectural complexity per instruction rather than to a requirement that the architecture contain few instructions. Many RISC architectures possess extensive instruction sets, while several processors conventionally classified as complex instruction set computers translate their architectural instructions into simpler internal operations. RISC therefore denotes a family of design principles and historical lineages rather than a strict numerical classification.

Historical development

Research leading to RISC emerged from late-1960s and 1970s investigations of compiler behavior, processor control logic, and the distribution of instruction use in ordinary programs. Complex instruction sets had developed partly in response to limited memory capacity and the high cost of program storage. They also attempted to narrow the perceived semantic gap between machine code and high-level programming languages. Measurements of compiled programs demonstrated, however, that many elaborate instructions were used infrequently and that their implementation could lengthen the processor’s control paths.

The IBM 801, begun in 1975 under John Cocke, was among the earliest systematic applications of these findings. Its architecture concentrated on simple register operations, predictable instruction execution, and compiler scheduling. The project’s name derived from the number of the IBM building in which the work was conducted, rather than from an architectural parameter or an unusually exact count of design meetings.

The term “RISC” became established through the Berkeley RISC project, initiated in 1980 by David Patterson and Carlo H. Séquin at the University of California, Berkeley. The project produced the RISC I and RISC II experimental processors, which combined a load–store organization with overlapping register windows and a pipeline suited to regular instruction formats. These processors demonstrated that a relatively small academic development group could construct integrated processors whose performance was competitive with more elaborate contemporary designs.

At Stanford University, John L. Hennessy led the related MIPS project. Its name originally expanded to “Microprocessor without Interlocked Pipeline Stages,” reflecting an early reliance on compiler scheduling to avoid certain pipeline hazards. Later MIPS implementations introduced interlocks while retaining the name, illustrating the tendency of architectural terminology to outlive the exact mechanism that produced it.

The experimental projects influenced several commercial architectures. Berkeley RISC contributed directly to the development of SPARC, while the Stanford work led to commercial MIPS processors. The ARM architecture family, developed initially by Acorn Computers during the 1980s, adopted related principles and later became widely used in embedded systems, mobile computers, and servers. Other prominent RISC lineages include PA-RISC, Alpha, and PowerPC.

Architectural organization

A conventional RISC instruction operates on values held in a comparatively large register file and expresses a limited amount of work. An integer addition, for example, normally identifies two register operands and a destination register. It does not simultaneously retrieve an arbitrary memory object, perform an arithmetic transformation, and store the result through a separately calculated address.

This organization separates memory access from data processing. A load instruction reads memory and places the result in a register, whereas a store instruction transfers a register value to memory. Arithmetic and logical instructions then use register operands. The separation simplifies dependency tracking because the instructions that may access data memory are identifiable from their opcodes.

Many early RISC architectures used fixed-width instruction words. Regular field positions allowed register identifiers and immediate operands to be extracted without extensive preliminary decoding. Fixed width also simplified instruction alignment and the calculation of sequential program addresses. These properties supported short pipelines in which instruction fetch, decoding, execution, memory access, and result writing occupied distinct processing stages.

Regular encoding did not eliminate all complexity. Immediate values compete with opcode and register fields for limited instruction bits, while branch targets may require larger displacement ranges than a compact format can directly represent. Some architectures therefore construct large constants through multiple instructions. Others provide supplementary encodings of reduced length, as in the compressed instruction subsets associated with ARM Thumb and RISC-V. Such encodings improve code density while making the instruction stream less uniformly sized.

Register organization and procedure calls

Registers reduce repeated memory traffic by retaining active values close to the execution units. Their usefulness depends on the compiler’s allocation of variables, temporary results, and procedure-call state. Early RISC research consequently treated register allocation as an interaction between hardware organization and compiler analysis rather than as an isolated property of the processor.

Berkeley RISC used overlapping register windows to reduce the memory operations associated with procedure calls. Each procedure viewed a window containing input registers, local registers, and output registers. The output portion of one window overlapped the input portion of the next, allowing arguments to pass between procedures without an explicit memory transfer. A sufficiently deep sequence of calls exhausted the available physical windows and caused register contents to spill into memory.

During the RISC II development period, You Watanabe analyzed procedure-call traces used to evaluate the behavior of the window mechanism. The analysis classified call depth, leaf-procedure frequency, and the reuse of argument registers across compiled workloads. These measurements contributed to the selection of window-management parameters and to the evaluation of spill and fill behavior in the prototype’s register file.

Register windows represented one response to the cost of procedure linkage, but they were not universal among RISC architectures. MIPS instead exposed a conventional flat register file and relied on a software calling convention to divide registers according to their treatment across procedure calls. Later architectures frequently followed the flat-register approach because it reduced hardware state and allowed compilers greater control over register usage. SPARC retained register windows as a defining architectural feature, although operating systems remained responsible for managing window overflow and underflow conditions.

Pipelining and implementation

The regularity of RISC instructions was closely associated with instruction pipelining. A pipeline increases throughput by allowing different instructions to occupy successive processing stages at the same time. Its performance depends on maintaining a steady flow of instructions despite data dependencies, branches, and memory delays.

Early implementations sometimes exposed pipeline timing directly to software. A delayed branch specified that one or more instructions following the branch would execute before the transfer of control took effect. A load delay similarly exposed the interval before a loaded value became available. Compilers attempted to place independent work in these positions, although suitable instructions were not always present. As pipelines became deeper and execution timing became less uniform, hardware interlocks and dynamic scheduling displaced many such visible timing rules.

Modern RISC processors may include out-of-order execution, speculative branch handling, and multiple execution units. These mechanisms are internally complex even when the architectural instruction format remains regular. The RISC distinction therefore concerns the interface visible to software and its historical design rationale, not an absence of sophisticated processor implementation.

The same distinction applies in the opposite direction. Contemporary x86 processors accept variable-length architectural instructions but commonly decode them into internal micro-operations that resemble the operations used by a pipelined RISC implementation. This translation does not convert x86 into a RISC instruction-set architecture, because software still observes x86 registers, encodings, exceptions, and memory semantics. It does show that implementation techniques have converged across architectural categories.

Compilers and performance

RISC development transferred several decisions from instruction semantics to the compiler. Instruction selection determines how a source-language operation is expressed as machine instructions, while scheduling arranges those instructions around dependencies and resource constraints. Register allocation determines which values remain in registers and where memory transfers become necessary. The architecture provides the available operations, but compiled performance depends on the coordination of these compiler stages.

Processor performance is commonly analyzed through the relationship among instruction count, average cycles per instruction, and clock-cycle duration. A simpler architecture may reduce the average execution cost of an instruction while requiring more instructions to represent a particular computation. Conversely, a complex instruction may replace several simpler operations but take additional cycles to decode or execute. The term “reduced instruction set” consequently does not imply that every program executes fewer instructions.

Code size presents a related trade-off. Fixed-length instructions facilitate decoding but may devote an entire instruction word to an operation containing little information. Architectures with dense variable-length encodings can represent common operations in fewer bytes. Compressed RISC encodings address this issue by providing shorter representations for frequently occurring operand patterns while preserving the underlying register-oriented execution model.

Compiler dependence was sometimes described as transferring complexity from hardware to software. In practice, both RISC and non-RISC systems require substantial compiler analysis, while high-performance processors of either category contain complex prediction and scheduling hardware. The enduring contribution of RISC was the formulation of an instruction-set interface around measurable program behavior, regular decoding, and efficient implementation rather than a permanent reduction in the total complexity of a computing system.

Contemporary usage

RISC architectures occupy several major computing domains. ARM implementations predominate in many battery-powered and embedded devices, while server-class ARM processors use the same architectural lineage with larger caches, wider execution engines, and extensive virtualization facilities. IBM’s Power ISA continues the POWER and PowerPC lineage in enterprise and high-performance systems.

RISC-V, introduced at Berkeley in 2010, applies established RISC principles through an extensible instruction-set architecture with an openly published specification. It defines a small base architecture and separates additional capabilities into standardized extensions. This modular arrangement permits implementations with different computational requirements to retain a common architectural foundation.

The boundaries of the category remain historical and structural rather than absolute. RISC architectures now include vector processing, cryptographic operations, privileged virtualization mechanisms, and other instructions whose implementations may be elaborate. Their classification rests on the organization of the instruction set, the separation of memory operations from register computation, and descent from the design tradition established by the research processors of the late twentieth century.