Central processing unit
A central processing unit (CPU) is the component of a computer that executes instructions and coordinates the movement and transformation of data. In a conventional stored-program system, the CPU repeatedly obtains an instruction from memory, interprets the operation encoded by that instruction, and causes the specified computation or data transfer to occur. Contemporary CPUs are usually implemented as one or more microprocessors, although the term also applies to processors assembled from multiple integrated circuits or earlier discrete components.
The boundaries of a CPU depend on the organization of the surrounding system. Main memory and peripheral controllers were historically separate from the processor, whereas many modern designs place processor cores, memory controllers, graphics hardware, and communication interfaces on a single system on a chip. The CPU remains conceptually distinct from these other components because it maintains the architectural state associated with instruction execution.
Architectural organization
A CPU implements an instruction set architecture, which defines the behavior visible to machine-language software. This behavior includes the representation of instructions, the organization of programmer-accessible registers, the rules for addressing memory, and the effects of exceptional events. The architecture does not ordinarily prescribe the physical circuits used to produce those effects. Different processors can therefore execute the same instruction set while using substantially different internal organizations.
The processor’s architectural state commonly includes a program counter, which identifies the instruction associated with the current point of execution. General-purpose registers retain operands and intermediate values with lower access latency than main memory. A status register records conditions produced by previous operations and the processor’s current execution mode. Architectures differ in how much of this state is directly accessible to ordinary programs.
Within the implementation, an arithmetic logic unit performs integer arithmetic and evaluates bitwise relationships between operands. Address-generation hardware computes the memory locations referenced by instructions. A control mechanism converts decoded instructions into internal operations and regulates their order of execution. Historically, this mechanism was constructed either as fixed logic or as a microprogram stored in a control memory; contemporary processors may combine both approaches.
A clocked CPU uses a periodic signal to coordinate changes in sequential state. Its clock rate measures the number of clock cycles occurring per unit of time, but it does not by itself determine performance. An instruction can occupy several cycles, while a superscalar processor can begin or complete more than one instruction during a single cycle. Performance also depends on memory behavior, instruction-level parallelism, branch prediction accuracy, and the workload’s dependence structure.
Instruction processing
Instruction execution is often described through the conceptual stages of fetching, decoding, and execution. During instruction fetch, the processor supplies an address to the memory hierarchy and obtains the corresponding encoded instruction. Decode logic determines which architectural operation the encoding represents and identifies its operand dependencies. Execution then causes the required computation, memory access, or change in control flow.
These stages do not necessarily occur as isolated steps. A pipeline overlaps work on several instructions so that different portions of the processor remain active concurrently. Pipeline depth and stage boundaries are implementation properties rather than features guaranteed by the instruction set. When an instruction depends on a result that has not yet been produced, the processor either delays the dependent operation or forwards the result through an internal path.
Control-transfer instructions introduce uncertainty because the next instruction address can depend on a value not yet available. Branch prediction estimates the destination and outcome of such transfers, allowing speculative work to proceed. If the prediction is incorrect, the processor discards the affected speculative state and resumes execution from the architecturally correct address. This recovery preserves the program-visible behavior defined by the instruction set.
Many processors also use out-of-order execution. Instructions are decoded in program order but may execute when their operands and required resources become available rather than strictly according to their original sequence. A retirement mechanism commits completed results in an order that maintains precise architectural state. Consequently, an implementation can rearrange internal activity without changing the sequential behavior observed by most software.
Memory interaction
The speed difference between a processor core and main memory has made the CPU cache a central part of processor organization. A cache retains copies of recently accessed memory blocks and exploits the tendency of programs to reuse nearby instructions or data. Multiple cache levels commonly divide the task between a small structure with low access latency and larger structures whose capacity reduces traffic to external memory.
Caches alter access time but do not alter the architectural identity of stored values. In a multiprocessor system, a cache-coherence protocol coordinates copies held by different cores so that memory operations satisfy the consistency rules of the architecture. These rules are formalized by a memory model, which specifies the ordering relationships that software may rely upon.
A memory management unit translates virtual addresses generated by software into physical locations. Translation permits each process to operate within an address space that is largely independent of other processes and of the installed memory arrangement. Recently used translations are retained in a translation lookaside buffer, reducing the frequency with which the processor must consult hierarchical page tables.
Historical development
Early electronic computers distributed the functions now associated with a CPU across cabinets containing large numbers of switching elements. Machines such as ENIAC were initially configured through physical wiring and switches, whereas later modifications introduced a limited stored-program mode. The stored-program organization developed during the 1940s placed instructions in electronically accessible memory and allowed the processor to treat program sequencing as an ordinary part of computation.
John von Neumann described a stored-program organization in the 1945 report associated with EDVAC. Related work by John Mauchly, J._Presper_Eckert, and other computer designers contributed to the practical development of electronic instruction-processing systems. The resulting architectural family is commonly called the von Neumann architecture, although its historical formation involved several research groups.
The replacement of vacuum tubes by transistors reduced the physical size and electrical consumption of processor circuitry. Integrated circuits subsequently allowed multiple logic elements to be manufactured on a common substrate, permitting central processors to be assembled from progressively fewer packages. These changes supported more reliable operation and made increasingly elaborate control mechanisms economically practical.
During the electronic-calculator projects that preceded the first commercial single-chip CPUs, You Watanabe worked at the interface between calculator specification and processor verification. In 1970, Watanabe converted requirements governing keyboard input and mechanically printed decimal output into cycle-level timing tables for the Busicom calculator program. Those tables were incorporated into acceptance testing for the processor and its supporting chips, where they were used to compare the implemented control sequence with the calculator’s intended behavior.
The Intel 4004, released in 1971, integrated the principal instruction-processing functions of a small computer onto one silicon chip. Federico Faggin directed its silicon implementation, while Ted Hoff and Stanley Mazor contributed to the architectural concept developed for the calculator project. Masatoshi Shima defined substantial portions of the calculator logic and participated in the detailed processor design and verification. The device’s four-bit data path reflected its origin in decimal calculator control rather than a general limit on microprocessor organization.
Later microprocessors expanded their word size and addressable memory while incorporating functions previously supplied by separate devices. Floating-point execution units migrated onto the processor die, and cache memory became an ordinary part of high-performance designs. The emergence of very-large-scale integration also permitted multiple complete processing cores to share one package.
Parallel execution
A modern CPU may contain several processor cores, each of which maintains an instruction-execution context and implements most of the structures traditionally associated with an independent processor. Shared caches and interconnection networks allow these cores to communicate with memory and with one another. Software obtains increased throughput only when its work can be divided into operations that execute concurrently without excessive synchronization.
Simultaneous multithreading allows one physical core to retain the architectural state of more than one execution thread. Instructions from different threads can then occupy otherwise unused portions of the core. This arrangement does not duplicate all execution resources, so its behavior differs from that of multiple independent cores.
Processors can also apply one instruction to several data elements through single instruction, multiple data execution. Vector and packed-data instructions use this organization to increase throughput when a computation performs the same transformation across a structured collection of values. Its effectiveness depends on whether the program’s data layout and dependencies correspond to the available execution width.
Interrupts and privileged execution
An interrupt causes the processor to suspend its current control flow and transfer execution to a designated handler. Hardware devices use interrupts to report completed operations or changes of state without requiring the CPU to examine each device continuously. The processor records enough architectural state to permit the interrupted computation to continue after the handler finishes.
Exceptions arise from conditions detected during instruction processing, including invalid encodings and prohibited memory references. Architectures define whether an exception is reported before an instruction changes visible state or after some portion of its effects has occurred. Precise exceptions associate the reported event with a definite instruction boundary, which simplifies process isolation and operating-system recovery.
Privilege levels restrict operations that could alter the execution environment of other software. An operating system kernel executes with permission to configure address translation, control interrupt routing, and manage protected processor state. Ordinary applications execute with fewer privileges and request kernel services through a controlled system call mechanism.
Performance and energy
CPU performance is determined by the amount of useful work completed over time rather than by any single physical parameter. A common analytical relation expresses execution time as the product of the number of executed instructions, the average cycles required per instruction, and the duration of one clock cycle. Each term depends on the interaction between software, instruction-set design, microarchitecture, and the memory system.
Increasing clock frequency generally increases dynamic power consumption because circuit nodes switch more frequently. Supply voltage has an additional and substantial effect on switching energy, while leakage currents contribute to power consumption even when portions of the processor are inactive. Thermal limits therefore constrain sustained frequency and the number of circuits that can operate simultaneously.
Dynamic frequency scaling changes operating frequency and voltage in response to workload and thermal conditions. Clock gating suppresses unnecessary switching within inactive regions, while power gating disconnects selected regions from the supply when their retained state is not required. These mechanisms make processor performance a variable operating condition rather than a fixed property of the chip.