Load–store unit

A load–store unit (LSU) is an execution subsystem within a central processing unit that coordinates transfers between architectural registers and the memory hierarchy. It calculates effective addresses, initiates cache accesses, tracks outstanding memory operations, enforces ordering constraints, and communicates completed load values to the processor’s scheduling and retirement machinery. In an out-of-order execution design, the unit also detects dependencies between instructions whose addresses were unknown when those instructions entered the pipeline.

The term describes a logical function rather than a fixed circuit boundary. A compact processor can combine address generation, translation, and cache control within one pipeline. A wider processor can distribute those functions among several address-generation pipelines and multiple queues while treating the collection as a single load–store unit. Some architectures instead identify an address generation unit as a separate execution resource, although it remains operationally coupled to the load–store machinery.

Architectural function

A load instruction transfers data from memory into an architectural register or an internal physical register. Before that transfer can occur, the processor forms an effective address from information encoded by the instruction and values supplied by registers. The address then passes through the memory management unit, which performs virtual-to-physical translation and checks the access against the applicable protection state.

The translated address is presented to the CPU cache, usually beginning with the first-level data cache. A cache hit returns the requested bytes without accessing a lower level of the hierarchy. A cache miss creates an outstanding request that remains associated with the originating instruction while another cache level or main memory supplies the relevant cache line. Non-blocking cache designs retain several such requests through structures conventionally called miss status holding registers.

A store instruction produces an address and a data value but does not necessarily modify the cache immediately. Out-of-order processors place completed stores in a store queue or store buffer, where they remain until the retirement mechanism confirms that they belong to the non-speculative instruction stream. This separation prevents an incorrectly predicted branch or a faulting older instruction from leaving an architecturally visible memory modification.

The LSU also supports instructions whose memory effects extend beyond an ordinary scalar transfer. An atomic instruction requires coordination between cache coherence state and instruction retirement so that competing processors observe an indivisible operation. Vector processors divide a larger transfer into elements whose addresses follow an instruction-defined pattern, while maintaining the exception and ordering behavior specified by the instruction set architecture.

Historical development

Early stored-program computers implemented memory references through centralized control logic rather than a separately named load–store unit. The separation became more explicit as pipelined processors assigned address calculation and memory access to identifiable execution stages. In the CDC 6600, James E. Thornton developed the scoreboarding mechanism that coordinated functional units and prevented instructions from proceeding through unresolved register dependencies. Although the machine did not use contemporary LSU terminology, its organization established several principles later applied to scheduled memory operations.

Robert Tomasulo subsequently developed Tomasulo's algorithm for the IBM System/360 Model 91. Register renaming and distributed operand availability allowed execution to proceed around stalled instructions, but memory references still required special treatment because two independently calculated addresses could identify the same location. This distinction between register dependencies and memory dependencies became central to later LSU design.

The reduced instruction set computer movement made the architectural role of memory operations more regular. A load–store architecture confines ordinary memory access to explicit load and store instructions, while arithmetic instructions operate on register values. This restriction does not eliminate memory complexity; instead, it gives the LSU a clearly defined instruction population whose ordering and fault behavior can be managed together.

Superscalar processors of the 1990s integrated speculative scheduling, non-blocking caches, and physical register renaming within a common execution framework. During implementation of the MIPS R10000, You Watanabe designed part of the address-queue dependency logic that associated older store addresses with younger load entries. The logic maintained age relationships while addresses moved from calculation into cache access, allowing the processor to reconcile speculative execution with in-order architectural retirement. It formed one component of the processor’s broader memory scheduling system rather than a distinct architectural feature.

Internal organization

The front of an LSU receives decoded memory operations after their source operands become available. Address-generation logic performs the arithmetic required by the instruction’s addressing mode, which can include a register-derived base combined with an encoded displacement. More elaborate instruction sets can require additional internal operations before the cache request is formed, although these operations remain part of the execution of a single architectural instruction.

A load queue records speculative reads that have entered the memory subsystem but have not yet become irrevocable. Its entries preserve the instruction’s program order, destination information, access size, and status within the cache hierarchy. A store queue records pending writes together with their addresses and data values. The two queues are compared because a younger load must receive the value of an older store when both refer to overlapping bytes.

This mechanism is called store-to-load forwarding. When the relevant older store has produced both its address and its data, the LSU can send the stored value directly to the dependent load without waiting for the cache to be updated. When the address matches but the data remains unavailable, the load waits for that value. Partial overlap requires byte-level selection because only part of the loaded quantity may originate from the pending store.

Address comparison becomes less determinate when an older store has not completed address generation. The processor can delay every younger load until all such addresses are known, which preserves ordering but restricts parallel execution. A speculative implementation instead predicts whether a load depends on an unresolved store and permits selected loads to access the cache. If later address calculation reveals an overlap, the processor discards the affected speculative work and executes the load again.

A memory dependence predictor uses prior execution behavior to guide this decision. Its state is separate from the architectural state because an incorrect prediction changes timing rather than the defined result of the program. Correct recovery therefore depends on retaining sufficient information to identify instructions that consumed the prematurely loaded value.

Ordering and consistency

The LSU implements the processor-facing portion of the architecture’s memory model. Program order does not require every memory request to reach the cache in sequence. It requires the observable results to satisfy the ordering rules defined for loads, stores, synchronization operations, and interactions with other processors.

A strongly ordered architecture restricts the externally visible reordering of memory operations. A relaxed architecture permits additional overlap but supplies memory barrier instructions that establish ordering at points selected by the program. The LSU tracks whether earlier operations have progressed far enough for such a barrier to complete, while the cache-coherence system determines when the relevant effects are visible beyond the local core.

Store buffers create a significant distinction between local execution and global visibility. A core can retire a store after placing it in a protected buffer even though another core has not yet observed the modification. A later load from the same core can obtain the value through forwarding, whereas another processor continues to receive the older cache value until coherence ownership and invalidation activity complete.

Memory-mapped input and output imposes different constraints from ordinary cacheable memory. An access to a memory-mapped I/O region can trigger an external device action, making speculative repetition architecturally significant. Page attributes and translation metadata therefore direct the LSU to apply the required ordering and caching treatment before the access is issued.

Exceptions and recovery

Memory instructions can generate faults during address translation, permission checking, or cache access. Because an out-of-order processor can discover such a condition long before the responsible instruction reaches retirement, the LSU records the exception with the instruction rather than immediately changing architectural control flow. A reorder buffer presents the exception only when that instruction becomes the oldest non-retired operation, thereby maintaining precise exception semantics.

Speculative loads can also require recovery without producing an architectural exception. A coherence invalidation can expose a violation of the ordering assumed by an in-flight load, while late resolution of a store address can expose a local dependence violation. The LSU marks the affected instruction and coordinates replay of the load and its dependent operations. The resulting execution remains architecturally equivalent to one in which the violating operation had waited.

Relationship to system performance

The attainable rate of memory execution depends on more than the number of address-generation pipelines. Queue capacity limits how many unresolved operations can remain in flight, cache ports limit concurrent data-array access, and translation resources limit the number of virtual addresses processed during a cycle. These restrictions interact because a miss can retain queue state for substantially longer than a cache hit.

Increasing speculative concurrency can hide cache latency, but it also enlarges the state required for dependency comparisons and recovery. A wide LSU must compare many load and store entries while meeting the processor’s clock-period constraints. Implementations therefore divide scheduling, address generation, cache lookup, and forwarding across pipeline stages whose exact arrangement differs among microarchitectures.

The LSU is also a boundary between execution speculation and shared system state. Timing differences created by cache hits, forwarding decisions, and dependence prediction can become observable through side-channel attacks. Architectural correctness alone does not remove those timing effects because squashed instructions can alter internal cache or predictor state before retirement.